1. Field of the Invention
The present invention relates to a semiconductor device and particularly to a two or more stage series-connected CMOS inverter among CMOS inverters using SGTs (surrounding gate transistors) that are vertical MOS transistors in which a columnar semiconductor is formed, the sidewall of the columnar semiconductor serves as a channel region, and a gate electrode formed around the channel region.
2. Description of the Related Art
In order to realize higher levels of integration and performance in semiconductor devices, SGTs (surrounding gate transistors) have been proposed that are vertical gate transistors having a columnar semiconductor layer formed on the surface of a semiconductor layer and a gate formed on the sidewall of the columnar semiconductor layer to surround it (for example, see Unexamined Japanese Patent Application KOKAI Publication No. H2-188966 and S. Watanabe et al., “A Novel Circuit Technology with Surrounding Gate Transistors (SGTs) for Ultra High Density DRAMs,” IEEE JSSC, Vol. 30, No. 9, September 1995). In a SGT, the drain, gate, and source are arranged in the vertical direction. Therefore, a SGT has a significantly reduced occupying area compared with conventional planar transistors.
An example of CMOS inverters using SGTs is disclosed in the Unexamined Japanese Patent Application KOKAI Publication No. H2-188966. FIG. 37A is a plane view of the CMOS inverter disclosed in the Unexamined Japanese Patent Application KOKAI Publication No. H2-188966 and FIG. 37B is a cross-sectional view at the section line A-A′ in FIG. 37A.
In FIGS. 37A and 37B, an N well 302 and a P well 303 are formed in a Si substrate 301. A columnar silicon layer 305 forming a PMOS (positive channel metal-oxide semiconductor) Qp is formed in the N well region 302 and a columnar silicon layer 306 forming an NMOS (negative channel metal-oxide semiconductor) Qn is formed in the P well region 303. A gate 308 and an element separation region 304 are each formed around the columnar silicon layer 305 and the columnar silicon layer 306. A P+ drain diffusion layer 310 formed in the lower part of the columnar silicon layer 305 forming a PMOS and an N+ drain diffusion layer 312 formed in the lower part of the columnar silicon layer 306 forming an NMOS are connected to an output terminal Vout. A P+ source diffusion layer 309 formed in the upper part of the columnar silicon layer 305 forming a PMOS is connected to a power supply potential Vcc via a Vcc wiring layer 314. An N+ source diffusion layer 311 formed in the upper part of the columnar silicon layer 306 forming an NMOS is connected to a ground potential Vss via a Vss wiring layer 315. The gate 308 shared by the PMOS and NMOS is connected to an input terminal (Vin) 316. With the above structure, a CMOS inverter is formed.
As an example of two or more stage series-connected CMOS inverters, FIG. 38A is a plane view of a two-stage CMOS inverter and FIG. 38B is a cross-sectional view at the section line A-A′ in FIG. 38A (see S. Watanabe et al., “A Novel Circuit Technology with Surrounding Gate Transistors (SGTs) for Ultra High Density DRAMs,” IEEE JSSC, Vol. 30, No. 9, September 1995).
In FIGS. 38A and 38B, a P+ diffusion layer 418 and an N+ diffusion layer 419 are formed in a silicon substrate. A power supply potential Vcc is given to the P+ diffusion layer 418 via a wiring layer 436 and a ground potential Vss is given to the N+ diffusion layer 419 via a wiring layer 435. Columnar silicon layers 411 to 414 composing PMOSs are formed on the P+ diffusion layer 418. Columnar silicon layers 415 to 417 composing NMOSs are formed on the N+ diffusion layer 419. The first-stage inverter is formed by PMOSs composed of the columnar silicon layers 413 and 414 and an NMOS composed of the columnar silicon layer 415. A common gate 422 is formed around the columnar silicon layers 413, 414, and 415. An input voltage to the first-stage inverter is given to the gate 422 via a wiring layer 433 and a contact 426 formed on the gate 422. The output voltage of the first-stage inverter is given to a wiring layer 437 via contacts 429 and 430 formed on the columnar silicon layers 413, 414, and 415.
The second-stage inverter is formed by PMOSs composed of the columnar silicon layers 411 and 412 and NMOSs composed of the columnar silicon layers 416 and 417. A gate 421 is formed around the columnar silicon layers 411 and 412. A gate 423 is formed around the columnar silicon layers 416 and 417. An input voltage to the second-stage inverter is given to the gate 421 via a wiring layer 437 and a contact 427 formed on the gate. An input voltage to the second-stage inverter is given to the gate 423 via a wiring layer 437 and a contact 428 formed on the gate. The output voltage of the second-stage inverter is given to a wiring layer 434 via contacts 431 and 432 formed on the columnar silicon layers 411, 412, 416, and 417.
In this two-stage inverter, a contact 424 connecting the wiring layer 436 to which a power supply potential Vcc is given and the P+ diffusion layer 418 and a contact 425 connecting the wiring layer 435 to which a ground potential Vss is given and the N+ diffusion layer 419 have large occupying areas. For this reason, the two-stage inverter has a large occupying area.
As another example of two or more stage series-connected CMOS inverters, FIG. 39A is a plane view of a CMOS inverter chain disclosed in the Unexamined Japanese Patent Application KOKAI Publication No. 2009-38226 and FIG. 39B is a cross-sectional view at the section line A-A′ in FIG. 39A.
In FIGS. 39A and 39B, columnar semiconductor layers 511, 512, 515, 516, 517, 518, 521, and 522 composing PMOSs and columnar semiconductor layers 513, 514, 519, and 520 composing NMOSs are formed on a silicon oxide film (SiO2 film). The first-stage inverter is formed by PMOSs composed of the columnar semiconductor layers 521 and 522 and an NMOS composed of the columnar semiconductor layer 520. A common gate 530 is formed around the columnar semiconductor layers 520, 521, and 522. A power supply potential is given to a diffusion layer formed in the upper parts of the columnar semiconductor layers 521 and 522 composing PMOSs via a wiring layer 535. A ground potential is given to a diffusion layer formed in the upper part of the columnar semiconductor layer 520 composing an NMOS via a wiring layer 534. The second-stage inverter is formed by PMOSs composed of the columnar semiconductor layers 517 and 518 and an NMOS composed of the columnar semiconductor layer 519. A common gate 529 is formed around the columnar semiconductor layers 517, 518, and 519. An input potential is given to the gate 529 via a lower wiring layer 525. A power supply potential is given to a diffusion layer formed in the upper parts of the columnar semiconductor layers 517 and 518 composing PMOSs via a wiring layer 533. A ground potential is given to a diffusion layer formed in the upper part of the columnar semiconductor layer 519 composing an NMOS via a wiring layer 534.
The above unit structure is repeated to form an inverter chain composed of the columnar semiconductor layers 511 to 522, lower wiring layers 523 to 526, gates 527 to 530, and wiring layers 531 to 535.
In the above prior art embodiment, the layout of diffusion layers and gate wiring composing a circuit is complex. NMOSs and PMOSs are alternately provided in a small area. Therefore, it is difficult to form a highly integrated inverter for use in a device as small as several tens nm. The Unexamined Japanese Patent Application KOKAI Publication No. 2009-38226 proposes parallel connection of the entire inverter circuit shown in FIG. 39 in order to increase the number of pillars formed in parallel. However, in such a case, even the portions making no direct contribution to the capability of the device such as element separation regions are repeatedly provided. This is not an efficient way of increasing the number of pillars formed in parallel.
As described above, the prior art structure of two or more stage series-connected CMOS inverters must be improved in terms of reduction in the occupying area.